1. Technical Field
The present invention relates to a semiconductor structure for substrate separation and a method for manufacturing the same, and more particularly, to a patterned semiconductor structure assisting in substrate separation using a chemical etching process.
2. Background
Recent breakthroughs in efficiency of high power III-nitride based Light Emitting Diodes (LEDs) paved the way for this promising device to move into general lighting applications earlier than expected. High power LED has potential to meet the dollar per lumen target for general lighting by providing comparable illumination per area with fewer LED dies, allowing for the reduction of fabrication and packaging cost. However, the selection of epitaxial substrate remains a key step in such products' design. A lattice matched substrate contributes to perfect crystal quality while a high thermal conductivity substrate improves light emitting efficiency.
Conventional LEDs with two electrodes disposed on the same side of the epitaxial layer unavoidably suffer from current crowding effect, while vertical LEDs with two electrodes placed on opposite sides of the epitaxial layer resolve the current crowding problem due to a shorter current path. In addition, with the integration of a high thermal conductivity substrate (usually metal), vertical LEDs not only dissipate heat efficiently so as to maintain a lower junction temperature, but also retain larger light emitting areas due to the device geometry.
In summary, high power LEDs with perfect crystal quality, high thermal conductivity substrates, and vertical device geometry are considered promising in the current market. Efforts have been made to achieve the abovementioned criteria by separating a conventional sapphire substrate from the epitaxial layers and replacing the sapphire substrate with a metal substrate. These steps can be categorized into a laser lift off (LLO) process and a chemical lift off (CLO) process.
U.S. Pat. No. 6,071,795 titled “Separation of Thin Film from Transparent Substrate by Selective Optical Processing” disclosed the LLO process. As shown in FIG. 1, a gallium nitride epitaxial layer 15 and its original sapphire substrate 19 are flip chip bonded to a carrier substrate 11 via an epoxy 13. A KrF excimer pulse laser 12 is irradiated from the surface of the transparent sapphire substrate, and is then absorbed at the shallow interface of the gallium nitride epitaxial layer 15; this shallow interface corresponds to a separation region 17. The sudden high temperature results in localized heating of the interface, while the short thermal diffusion length, on the order of a micrometer, prevents substantial heating of the active region of the heterostructure, thereby circumventing thermal damage and permitting lift-off of the gallium nitride layer 15. In the separation region 17, a few nanoseconds at temperatures of over 1000 degrees Celsius is sufficient to induce decomposition of the interfacial GaN to liquid Ga metal and nitrogen gas, without causing immediate separation of the growth substrate. Although the decomposition reaction occurs at limited depth and can prevent damages from extending to the crucial light emitting active region, the sudden temperature rise in the interface (i.e. the sapphire and gallium nitride interface) with large difference in thermal expansion coefficients generates high density threading dislocation, which leads to serious wafer cracking and undesired residual strain in the thin film that may compromise the crystal quality of the active region. In addition, the thermal strain can cause the sidewall passivation layer to peel off, degrading the structural integrity of the LEDs.
The CLO process is comparably milder in terms of heat-induced strain at the interface. Furthermore, the selectivity nature of wet etching provides fast and economical options for achieving the substrate separation in LED devices. Jun-Seok Ha et al. published an article titled “The Fabrication of Vertical Light-Emitting Diodes Using Chemical Lift-off Process” in IEEE Photonics Technology Letters, Volume 20, No. 3, February 2008, proposing the use of a sacrificial CrN layer 22 shown in FIG. 2 to separate the gallium nitride thin film and the sapphire substrate 21. A gallium nitride epitaxial layer, including an n-GaN 23, an active layer 24, and a p-GaN 25, is grown on a CrN layer 22 disposed on an original sapphire substrate 21. A p-GaN contact 26 is formed on top of the p-GaN 25 followed by a deposition of a metal substrate 27. The issues with this technique are twofold: 1) gallium nitride crystal quality is seriously compromised since the CrN layer is not a single crystal template for the following gallium nitride epitaxy, and 2) it is almost impossible to utilize a single continuous sacrificial layer design to lift off the epitaxial layer on a large size wafer.
Another article titled “Transferring Thin Film Gallium Nitride LED Epi-Structure to the Copper Substrate by Chemical Lift-Off Technology” and published in Electrochemical and Solid-State Letters Vol. 14, Issue 7, H281-H284 in 2011 by Ray-Hua Horng et al. discloses a method combining an oxide-patterned sacrificial (OPS) layer and an epitaxial lateral overgrowth (ELOG) technique to form a self-detached thin film from the sapphire substrate. As shown in FIG. 3, an OPS layer 33 is patterned on a sapphire substrate 31. An epitaxial gallium nitride layer 35 is then deposited using an ELOG technique, followed by the deposition of a reflective mirror layer 37 and the electroplating of a copper layer 39. Hydrofluoride (HF) is used to remove the OPS layer 33 and render a high stress field concentrated at the post-etch interface, that is, the interface between the sapphire substrate 31 and the gallium nitride epitaxial layer 35. In this manner, the thin film is easily detached from the underlying sapphire substrate 31 and successfully transferred to the copper layer 39. Strain release facilitates the thin film separation process but the ELOG process requires sophisticated crystal growth proficiency with complex growth parameters. Although a low defect density region in the coalescence front is one advantage of the ELOG process, the desired crystal quality region is not continuous and represents only one fifth of the entire wafer surface region.
Ke Yan Zang et al. published an article titled “A New Method For Lift-Off of III-Nitride Semiconductor For Heterogeneous Integration” in Nanoscale Research Letters Vol. 5, 1051-1056 in 2010. A structure designed for a CLO process is shown in FIG. 4. A buffer gallium nitride layer 43 is first deposited on a sapphire substrate 41, and a layer of silicon dioxide is deposited on the buffer gallium nitride layer 43. An anodized alumina (AAO) is used (not shown) to generate an oxide template with nano-scaled pattern and transfer the pattern onto the underlying silicon dioxide layer to form a patterned oxide layer 45. A nano-epitaxial lateral overgrowth (NELO) is then performed to grow gallium nitride thin film 47, followed by a routine HF wet etch. After the silicon dioxide layer is removed, the gallium nitride thin film 47 can be self-released due to the large strain field present at the corners of the gallium nitride thin film positioned in the depression of the silicon dioxide pattern 45. The NELO technique used in this disclosure is more sophisticated than the conventional ELOG, because in adopting metalorganic chemical vapor deposition (MOCVD) as a means for crystal growth, the maintenance of a lamellar supply of the precursor or reactant is crucial. A planar surface is the most desirable geometry for MOCVD because it provides a flat and open reaction platform. Other morphologies will unduly increase the difficulty of the epitaxial growth. Inevitably, any epitaxy performed on a nano-scaled patterned surface suffers from major issues preventing this method from achieving a reasonable yield.
Chia-Feng Lin et al. discloses another CLO method combining a sacrificial layer, selective epitaxial growth, and a crystallographic wet etching approach as published in Applied Physics Express Vol. 3, 092101, in 2010, and the article titled “Chemical Lift-Off Process for Blue Light-Emitting Diodes.” The structure proposed in the prior art, as shown in FIG. 5, comprises a truncated-triangle-striped sapphire substrate 51 deposited with an AlN buffer/sacrificial layer 58, an n-GaN layer 53, a multi-quantum well active layer 54, a p-GaN 55, and a transparent contact layer 56. Two distinct crystallographic plans {10 12} and {10 15} constitute the two faces of the truncated triangles due to the selective etching using hot sulfuric acid and phosphoric acid. The etchant enters the truncated triangle region through a channel 57 opened by a laser scribing process. The presence of the air voids 52 is partly due to the truncated-triangle pattern on the sapphire substrate 51 and partly the result of epitaxial selective growth in the n-GaN layer 53. Hot potassium hydroxide solution is then applied through the channel 57 and performs a crystallographic etch in the n-GaN layer 53 followed by a lateral etch of the buffer/sacrificial AlN layer 58. Inclined GaN facets {10 1 1} act as an etch stop preventing damage to the active layer. The thin film separation occurs at the completion of the lateral AlN etch. This technique further generates a roughened post-etch surface on the n-GaN layer 53, which corresponds to a common design feature in optical devices to enhance light extracting efficiency. Easy etching process makes the disclosed method appealing; however, in addition to the complex structure, the unavoidable compromise of the crystal quality still exists due to the lattice mismatch between AlN and GaN.
International application No. PCT/GB2007/001011 titled “Growth Method Using Nanostructure Compliant Layers and HVPE for Producing High Quality Compound Semiconductor Materials” disclosed a sophisticated Hydride Vapor Phase Epitaxy (HVPE) technique in growing a high quality semiconductor layer 69 on an underlying template with nano columns 65 as shown in FIG. 6. This article demonstrates a highly sophisticated epitaxial growth technique so as to perform a high quality ELOG on a nanostructure template followed by a separation process between the high quality semiconductor layer 69 from the nano-scaled compliant layer. The distinction between this international application and the aforementioned ELOG and NELO prior arts lies in the material used as the ELOG template. Nano columns consisting of a compound semiconductor material are used in the international application while silicon dioxide stripe patterns are used in the other two prior arts. A lateral growth on the side walls of the compound semiconductor nano columns 65 can be anticipated, creating an ever-changing template underneath the top high quality semiconductor layer 69.
In light of the stated prior arts, the semiconductor structure proposed in one embodiment of the present invention used for substrate separation in LEDs comprises 1) an array structure which promotes an effective CLO process to increase the penetration of the chemical etchant; and 2) a pseudo-planar template that effectively reduces the difficulty of the epitaxial growth and increases the product yield.